This application claims the priority of Korean Patent Application No. 2003-84957, filed on Nov. 27, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a memory test circuit and a test system, and more particularly, to a test circuit and a test system having a built-in self test (BIST) unit for testing failure a highly integrated memory.
2. Description of the Related Art
Today, chips are designed and manufactured for deep sub-micron (DSM) technology, and more memories are embedded such that memory yield has a serious effect on the yield of the entire chip. Accordingly, in order to improve the yield of chips, a repairable memory is needed.
In addition, as the degree of integration of a semiconductor device increases and the functions become more complicated, a variety of methods for efficiently testing such semiconductor devices are being developed. In particular, in order to efficiently test a memory embedded in a semiconductor device, a method referred to as a memory BIST (hereinafter referred to as ‘BIST’), has been developed. By using a circuit implementing a memory test algorithm, an embedded memory is tested according to this method.
More recently, unlike the BIST testing a memory, built-in redundancy analysis (BIRA) technology, by which, after testing an embedded repairable memory by using the BIST test method, a failure is analyzed and information to performing repair is extracted, has been introduced.
That is, by using the BIST, a memory is tested and information on a failure is stored, and then according to built-in self repair (BISR), repair is performed and by using a scan chain the result is output.
However, when the BIST is used to repair a highly integrated memory capable of repairing a row and column failure in order to improve yield, the overhead of the BIST increases such that design of the BIST becomes difficult.